1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device that includes an impedance-adjustable output buffer and a method of adjusting a characteristic of the semiconductor device.
2. Description of Related Art
In recent years, extremely high data transfer rates have been needed for data transfer between semiconductor devices (such as between a CPU and a memory). For implementation, input/output signals have become increasingly smaller in amplitude. Input/output signals of smaller amplitudes make extremely severe the accuracy requirement for the impedances of output buffers.
The impedance of an output buffer not only varies with the process condition during manufacturing, but also is affected by changes in ambient temperature and power supply voltage in actual use. When an output buffer needs a high impedance accuracy, one having an impedance adjustment function is employed. The impedance adjustment to such an output buffer is typically made by using an output impedance adjustment circuit called “calibration circuit.”
The calibration circuit includes a replica buffer that has the same configuration as that of the output buffer. In a calibration operation, with an external resistor connected to a calibration terminal, the voltage appearing on the calibration terminal is compared with a reference voltage, and the replica buffer is adjusted accordingly in impedance. The adjustment of the replica buffer is reflected on the output buffer, whereby the impedance of the output buffer is adjusted to a desired value (refer to Japanese Patent Application Laid-Open No. 2010-21994).
The impedance of the replica buffer is adjusted stepwise in synchronization with a clock signal. More specifically, both the voltage comparison of a comparator and the adjustment of the impedance based on the comparison result are performed in synchronization with the clock signal. The higher the frequency of the clock signal, the more difficult it is to secure a time for the comparator to perform the voltage comparison (hereinafter, referred to as “determination time”). Typically, the accuracy of detection of a potential difference by the comparator tends to deteriorate as the determination time decreases.
To address such a problem, a frequency division circuit may be used to reduce the clock signal in frequency so that the impedance can be adjusted in synchronization with the clock signal of reduced frequency. Too low a frequency of the clock signal, however, makes the calibration period long.